Creating an array of structs with macro in Systemverilog -

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i've created module (example) 2 in , 2 out-puts. definition of every in , output delcared through macro.

is possible create bit more elegant (later usability)? array of inputs , outputs (name(i), in(i), out(i))?

it helpful, because later using more out , inputs , there possbility using later loops access in/outputs more elegant.

top:

`include "macro.sv"  module top (in_0, in_1, out_0, out_1);      `struct_i(in_0_temp,  10);     `struct_i(in_1_temp,  22);     `struct_i(out_0_temp,  55);     `struct_i(out_1_temp,  99);      input   `struct(in_0_temp)      in_0;     input   `struct(in_1_temp)      in_1;     output  `struct(out_0_temp)     out_0;     output  `struct(out_1_temp)     out_1;  ...      endmodule

macro.sv :

`define struct(name) \ struct_i_``name``  `define struct_i(name, data) \ typedef struct packed { \   logic [data:0]            info; \   logic                     test1; \   logic                     test2; \     } `struct(name)

there no way array because, definition, array collection of uniformly typed variables. access dynamic index value requires each element have identical layout. not work simple bit vectors of different lengths. synthesizable option declare info max size , hope unused bits optimized away.


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